A semiconductor memory device receives a data strobe signal as well as data from a memory controller. The data strobe signal synchronizes the semiconductor memory device to the memory controller upon receiving data so as to ensure safe data transfer. The semiconductor memory device stores the received data in a memory cell by using a write driving device.
FIG. 1 shows a conventional write driving device.
In FIG. 1, the conventional write driving device includes a data input clock generation unit 1, a data alignment unit 2, and a driving unit 3.
When a write command WTCMD is inputted, the data input clock generation unit 1 generates a data input clock DINCLK which is enabled at a preset timing of a clock. The data alignment unit 2 receives data D1 to D4 serially inputted in response to a transition timing of a data strobe signal DQS to align the received data D1 to D4 in parallel and outputs parallel data PD<1:4>. The driving unit 3 outputs the parallel data PD<1:4> as global line data GIOD<1:4> in response to the data input clock DINCLK.
The operation of the conventional write driving device will be described below with reference to FIGS. 2-3.
FIGS. 2-3 are timing diagrams illustrating the operation of the write driving device of FIG. 1, based on a minimum input timing and a maximum input timing of the data strobe signal, which are defined in the Joint Electron Device Engineering Council (JEDEC). For purposes of illustration, a write latency is 1 is assumed.
Referring to FIG. 2, when the write command WTCMD is inputted at time T0 of the clock CLK, the data strobe signal DQS is inputted after 0.75tCK from time T1 of the clock CLK. The input of the data strobe signal DQS after 0.75tCK from time T1 of the clock CLK is referred to as a minimum input timing tDQSSmin of the data strobe signal DQS. When the data strobe signal DQS is inputted, the data alignment unit 2: receives the data D1 to D4 in response to the transition of the data strobe signal DQS; parallelizes the data D1 to D4 at a timing when the reception of the data D1 to D4 is completed; and outputs the parallel data PD<1:4>. The data input clock generation unit 1 generates the data input clock DINCLKP, which is enabled to a high level at a preset timing after the input timing of the write command TWCMD, that is, during a duration TA. The driving unit 3 outputs the parallel data PD<1:4> as the global line data GIOD<1:4> in response to the data input clock DINCLKP.
Referring to FIG. 3, the data strobe signal DQS is inputted after 1.25tCK from time T1 of the clock CLK when the write command WTCMD is inputted at time T0 of the clock CLK. The input of the data strobe signal DQS after 1.25tCK from time T1 of the clock CLK is referred to as a maximum input timing tDQSSmax of the data strobe signal DQS. When the data strobe signal DQS is inputted, the data alignment unit 2: receives the data D1 to D4 in response to the transition of the data strobe signal DQS; parallelizes the data D1 to D4 at a timing when the reception of the data D1 to D4 is completed; and outputs the parallel data PD<1:4>. The data input clock generation unit 1 generates the data input clock DINCLKP, which is enabled to a high level at a preset timing after the input timing of the write command WTCMD, that is, during a duration TA. The driving unit 3 outputs the parallel data PD<1:4> as the global line data GIOD<1:4> in response to the data input clock DINCLKP.
Comparing FIGS. 2 and 3, the timing of generating the parallel data PD<1:4> is varied depending on the input timing of the data strobe signal DQS, whereas the output timing of the parallel data PD<1:4> to the global line data GIOD<1:4>, that is, the timing of generating the data input clock DINCLKP, does not vary. This occurs because it is specified that the data input clock DINCLKP should be enabled at an assigned timing. So long as the data strobe signal DQS is inputted within the range of the minimum input timing tDQSSmin and the maximum input timing tDQSSmax, the margin for allowing the parallel data PD<1:4> to be outputted as the global line data GIOD<1:4> is ideally ensured even though the generation timing of the data input clock DINCLKP did not vary.
However, even if the data strobe signal DQS is commanded to be inputted within the minimum and maximum input timings tDQSSmin, tDQSSmax, the actual input of the data strobe signal DQS may still experience a delay due to the internal environment factors of the semiconductor memory device, e.g., voltage, temperature, loading, etc. Then, the data D1 to D4 delayed by the additional delay time of the data strobe signal DQS will be inputted when there were an additional delay in the data strobe signal DQS due to the undesirable factors. Consequently, the generation timing of the parallel data PD<1:4> will also be delayed additionally.
For example, now referring to FIG. 4, when the data strobe signal DQS were to be inputted at the maximum input timing tDQSSmax but was delayed by αtCK due to the internal environment factors, the delayed data strobe signal DQSD will delay the input timing of the data D1 to D4 that will in turn delay the generation timing of the parallel data PD<1:4>. Since the data input clock DINCLKP would be enabled during the assigned duration TA, which does not vary regardless of the delayed input timing of the data D1 to D4, the margin for outputting the parallel data PD<1:4> as the global line data GIOD<1:4> will then become insufficient. The parallel data PD<1:4> then will not completely transfer to the global lines. This problem will only get more serious as the bit number of data for transfer increases.
In addition, the external environment factors (e.g., temperature, voltage, loading, etc.) will also cause the problems of delay as described above as the frequency of the semiconductor device increases and the operating voltage decreases, and such phenomenon may occur when the data strobe signal DQS outputted from the memory controller is not inputted between the minimum input timing tDQSSmin and the maximum input timing tDQSSmax.